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ltc2753 1 2753f typical application features applications description dual current output 12-/14-/16-bit softspan dacs with parallel i/o the ltc ? 2753 is a family of dual 12-, 14-, and 16-bit multiplying parallel-input, current-output dacs. these dacs operate from a single 2.7v to 5.5v supply and are all guaranteed monotonic over temperature. the ltc2753a-16 provides 16-bit performance (1lsb inl and dnl) over temperature without any adjustments. these softspan? dacs offer six output rangestwo unipolar and four bipolarthat can be programmed through the parallel interface, or pinstrapped for operation in a single range. the ltc2753 dacs use a bidirectional input/output parallel interface that allows readback of any on-chip register. a power-on reset circuit resets the dac outputs to 0v when power is initially applied. a logic low on the clr pin asyn- chronously clears the dacs to 0v in any output range. the parts are speci? ed over commercial and industrial temperature ranges. dual 16-bit v out dac with software-selectable ranges six programmable output ranges unipolar: 0v to 5v, 0v to 10v bipolar: 5v, 10v, 2.5v, C2.5v to 7.5v maximum 16-bit inl error: 1 lsb over temperature low 1a (maximum) supply current guaranteed monotonic over temperature low glitch impulse 1nv?s 2.7v to 5.5v single supply operation 2s settling time to 1 lsb parallel interface with readback of all registers asynchronous clr pin clears dac outputs to 0v in any output range power-on reset to 0v 48-pin 7mm 7mm qfn package high resolution offset and gain adjustment process control and industrial automation automatic test equipment data acquisition systems ltc2753-16 integral nonlinearity (inl) , lt, ltc and ltm are registered trademarks of linear technology corporation. softspan is a trademark of linear technology corporation. all other trademarks are the property of their respective owners. code 0 C1.0 inl (lsb) C0.8 C0.4 C0.2 0.0 1.00.4 16384 32768 C0.6 0.6 0.8 0.2 49152 65535 2753 ta01b 25 c 90 c C45 c v dd = 5v v ref = 5v 10v range + C C + C + span i/o data i/o dac a 46 47 r1r2 21 48 39 40 ltc2753-16 r fba i out1a v outa v outb i out2a r vosa r vosb i out2b i out1b r fbb 45 4 4443 32 42 41 r ofsb refb refa 150pf 15pf15pf 1/2 lt1469 1/2 lt1469 1/2 lt1469 r com r in r ofsa v ref 5v dac b 2753 ta01 16 3 i/o port i/o port downloaded from: http:///
ltc2753 2 2753f 48 47 46 45 44 43 42 41 40 39 38 37 13 14 15 16 17 18 19 20 21 22 23 24 r com r in s2 i out2a gnd d11d10 d9d8 d7 d6 d5 updread d /s s0i out2b gndnc nc nc nc nc nc 12 3 4 5 6 7 8 9 1011 12 3635 34 33 32 31 30 29 28 27 26 25 d4d3 v dd nc a1a0 gnd clr mspan d2d1 d0 refa r ofsa r fba i out1a r vosa r vosb i out1b r fbb r ofsb refbs1 wr 49 ltc2753-12 uk package 48-lead (7mm 7mm) plastic qfn t jmax = 125c, ja = 29c/w exposed pad (pin 49) is gnd, must be soldered to pcb r com r in s2 i out2a gnd d13d12 d11 d10 d9d8 d7 updread d /s s0i out2b gndnc nc nc nc d0 d1 d6d5 v dd nc a1a0 gnd clr mspan d4d3 d2 refa r ofsa r fba i out1a r vosa r vosb i out1b r fbb r ofsb refbs1 wr ltc2753-14 uk package 48-lead (7mm 7mm) plastic qfn 48 47 46 45 44 43 42 41 40 39 38 37 13 14 15 16 17 18 19 20 21 22 23 24 12 3 4 5 6 7 8 9 1011 12 3635 34 33 32 31 30 29 28 27 26 25 49 t jmax = 125c, ja = 29c/w exposed pad (pin 49) is gnd, must be soldered to pcb r com r in s2 i out2a gnd d15d14 d13 d12 d11 d10 d9 updread d /s s0i out2b gndnc nc d0 d1 d2 d3 d8d7 v dd nc a1a0 gnd clr mspan d6d5 d4 refa r ofsa r fba i out1a r vosa r vosb i out1b r fbb r ofsb refbs1 wr ltc2753-16 uk package 48-lead (7mm 7mm) plastic qfn 48 47 46 45 44 43 42 41 40 39 38 37 13 14 15 16 17 18 19 20 21 22 23 24 12 3 4 5 6 7 8 9 1011 12 3635 34 33 32 31 30 29 28 27 26 25 49 t jmax = 125c, ja = 29c/w exposed pad (pin 49) is gnd, must be soldered to pcb absolute maximum ratings i out1x , i out2x , r com to gnd .................................0.3v r vosx , r fbx , r ofsx , r in , ref x to gnd ...................15v v dd to gnd .................................................. C0.3v to 7v digital inputs and digital i/o to gnd ..........................C0.3v to v dd +0.3v (max 7v) (notes 1, 2) pin configuration order information lead free finish tape and reel part marking* package description temperature range ltc2753cuk-12#pbf ltc2753cuk-12#trpbf ltc2753uk-12 48-lead (7mm 7mm) plastic qfn 0c to 70c ltc2753iuk-12#pbf ltc2753iuk-12#trpbf ltc2753uk-12 48-lead (7mm 7mm) plastic qfn C40c to 85c ltc2753cuk-14#pbf ltc2753cuk-14#trpbf ltc2753uk-14 48-lead (7mm 7mm) plastic qfn 0c to 70c ltc2753iuk-14#pbf ltc2753iuk-14#trpbf ltc2753uk-14 48-lead (7mm 7mm) plastic qfn C40c to 85c ltc2753bcuk-16#pbf ltc2753bcuk-16#trpbf ltc2753uk-16 48-lead (7mm 7mm) plastic qfn 0c to 70c ltc2753biuk-16#pbf ltc2753biuk-16#trpbf ltc2753uk-16 48-lead (7mm 7mm) plastic qfn C40c to 85c ltc2753acuk-16#pbf ltc2753acuk-16#trpbf ltc2753uk-16 48-lead (7mm 7mm) plastic qfn 0c to 70c ltc2753aiuk-16#pbf ltc2753aiuk-16#trpbf ltc2753uk-16 48-lead (7mm 7mm) plastic qfn C40c to 85c consult ltc marketing for parts speci? ed with wider operating temperature ranges. *the temperature grade is identi? ed by a label on the shipping container. consult ltc marketing for information on non-standard lead based ? nish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel speci? cations, go to: http://www.linear.com/tapeandreel/ operating temperature range ltc2753c ..................................................... 0c to 70c ltc2753i .................................................. C40c to 85c maximum junction temperature........................... 125c storage temperature range ................... C65c to 150c downloaded from: http:///
ltc2753 3 2753f electrical characteristics v dd = 5v, v ref = 5v unless otherwise speci? ed. the denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. symbol param eter conditions ltc2753-12 ltc2753-14 ltc2753b-16 ltc2753a-16 units min typ max min typ max min typ max min typ max static performance resolution 12 14 16 16 bits monotonicity 12 14 16 16 bits dnl differential nonlinearity 1 1 1 0.2 1 lsb inl integral nonlinearity 1 1 2 0.4 1 lsb ge gain error all output ranges 0.5 2 1.5 5 20 4 14 lsb ge tc gain error temp- erature coef? cient gain/ temp 0.6 0.6 0.6 0.6 ppm/c bze bipolar zero error all bipolar ranges 0.2 1 0.6 3 12 2 8 lsb bzs tc bipolar zero temp- erature coef? cient 0.5 0.5 0.5 0.5 ppm/c psr power supply rejection v dd = 5v, 10% v dd = 3v, 10% 0.025 0.06 0.1 0.25 0.4 1 0.03 0.1 0.20.5 lsb/v i lkg i out1 leakage current t a = 25c t min to t max 0.05 2 5 0.05 2 5 0.05 2 5 0.05 2 5 na c iout1 output capacitance full-scalezero scale 7545 7545 7545 7545 pfpf symbol parameter conditions min typ max units resistances (note 3) r1, r2 reference inverting resistors (note 4) 16 20 k r ref dac input resistance 81 0 k r fb feedback resistor (note 3) 81 0 k r ofs bipolar offset resistor (note 3) 16 20 k r vos offset adjust resistor 800 1000 k dynamic performance output settling time 0v to 10v range, 10v step. to 0.0015% fs (note 5) 2 s glitch impulse (note 6) 1 nv?s digital-to-analog glitch impulse (note 7) 1 nv?s multiplying feedthrough error 0v to 10v range, v ref = 10v, 10khz sine wave 0.5 mv thd total harmonic distortion (note 8) multiplying C110 db output noise voltage density (note 9) at i out1 13 nv/ ? h ? z v dd = 5v, v ref = 5v unless otherwise speci? ed. the denotes speci? cations that apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. downloaded from: http:///
ltc2753 4 2753f symbol parameter conditions min typ max units power supplyv dd supply voltage 2.7 5.5 v i dd supply current, v dd digital inputs = 0v or v dd 0.5 1 a digital inputsv ih digital input high voltage 3.3v v dd 5.5v 2.7v v dd < 3.3v 2.4 2 vv v il digital input low voltage 4.5v < v dd 5.5v 2.7v v dd 4.5v 0.80.6 vv i in digital input current v in = gnd to v dd 1 a c in digital input capacitance v in = 0v (note 10) 6p f digital outputsv oh i oh = 200a v dd C 0.4 v v ol i ol = 200a 0.4 v timing characteristics the denotes speci? cations that apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. symbol parameter conditions min typ max units v dd = 4.5v to 5.5v write and update timing t 1 i/o valid to wr rising edge set-up 7n s t 2 i/o valid to wr rising edge hold 7n s t 3 wr pulse width low 15 ns t 4 upd pulse width high 15 ns t 5 upd falling edge to wr falling edge no data shoot-through 0n s t 6 wr rising edge to upd rising edge (note 10) 0n s t 7 d /s valid to wr falling edge set-up time 7n s t 8 wr rising edge to d /s valid hold time 7n s t 9 a1-a0 valid to wr falling edge setup time 5n s t 10 wr rising edge to a1-a0 valid hold time 0n s t 11 a1-a0 valid to upd rising edge setup time 9n s t 12 upd falling edge to a1-a0 valid hold time 7n s readback timing t 13 wr rising edge to read rising edge 7n s t 14 read falling edge to wr falling edge (note 10) 20 ns t 15 read rising edge to i/o propagation delay c l = 10pf 40 ns t 26 a1-a0 valid to read rising edge setup time 20 ns t 27 read falling to a1-a0 valid hold time (note 10) 0n s electrical characteristics v dd = 5v, v ref = 5v unless otherwise speci? ed. the denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. downloaded from: http:///
ltc2753 5 2753f symbol parameter conditions min typ max units t 17 upd valid to i/o propagation delay c l = 10pf 26 ns t 18 d /s valid to read rising edge (note 10) 7n s t 19 read rising edge to upd rising edge no update 0n s t 20 upd falling edge to read falling edge no update 0n s t 22 read falling edge to upd rising edge (note 10) 7n s t 23 i/o bus hi-z to read rising edge (note 10) 0n s t 24 read falling edge to i/o bus active (note 10) 20 ns clr timing t 25 clr pulse width low 15 ns v dd = 2.7v to 3.3v write and update timing t 1 i/o valid to wr rising edge set-up 15 ns t 2 i/o valid to wr rising edge hold 15 ns t 3 wr pulse width low 30 ns t 4 upd pulse width high 30 ns t 5 upd falling edge to wr falling edge no data shoot-through 0n s t 6 wr rising edge to upd rising edge (note 10) 0n s t 7 d /s valid to wr falling edge set-up time 7n s t 8 wr rising edge to d /s valid hold time 7n s t 9 a1-a0 valid to wr falling edge setup time 7n s t 10 wr rising edge to a1-a0 valid hold time 0n s t 11 a1-a0 valid to upd rising edge setup time 15 ns t 12 upd falling edge to a1-a0 valid hold time 15 ns readback timing t 13 wr rising edge to read rising edge 10 ns t 14 read falling edge to wr falling edge (note 10) 35 ns t 15 read rising edge to i/o propagation delay c l = 10pf 53 ns t 26 a1-a0 valid to read rising edge setup time 35 ns t 27 read falling to a1-a0 valid hold time (note 10) 0n s t 17 upd valid to i/o propagation delay c l = 10pf 43 ns t 18 d /s valid to read rising edge (note 10) 12 ns t 19 read rising edge to upd rising edge no update 0n s t 20 upd falling edge to read falling edge no update 0n s timing characteristics the denotes speci? cations that apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. downloaded from: http:///
ltc2753 6 2753f symbol parameter conditions min typ max units v dd = 2.7v to 3.3v t 22 read falling edge to upd rising edge (note 10) 10 ns t 23 i/o bus hi-z to read rising edge (note 10) 0n s t 24 read falling edge to i/o bus active (note 10) 35 ns clr timing t 25 clr pulse width low 20 ns note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: continuous operation above the speci? ed maximum operating junction temperature may impair device reliability. note 3 : because of the proprietary softspan switching architecture, the measured resistance looking into each of the speci? ed pins is constant for all output ranges if the i out1x and i out2x pins are held at ground. note 4: r1 is measured from r in to r com ; r2 is measured from refa to r com . note 5: using lt1469 with c feedback = 15pf. a 0.0015% settling time of 1.7s can be achieved by optimizing the time constant on an individual basis. see application note 74, component and measurement advances ensure 16-bit dac settling time. note 6: measured at the major carry transition, 0v to 5v range. output ampli? er: lt1469; c fb = 27pf. note 7. full-scale transition; ref = 0v. note 8. ref = 6v rms at 1khz. 0v to 5v range. dac code = fs. output ampli? er = lt1469. note 9. calculation from v n = ? 4 ? k ? t ? r ??? b, where k = 1.38e-23 j/k (boltzmann constant), r = resistance (), t = temperature (k), and b = bandwidth (hz). note 10. guaranteed by design. not production tested. timing characteristics the denotes speci? cations that apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. downloaded from: http:///
ltc2753 7 2753f v ref (v) C10 C8 0 4 4 C6 2 2 6 8 10 2751 g09 v dd = 5v 5v range C1.0 inl (lsb) C0.8 C0.4 C0.2 0.0 1.00.4 C0.6 0.6 0.8 0.2 +dnl Cdnl +dnl Cdnl code 0 C1.0 inl (lsb) C0.8 C0.4 C0.2 0.0 1.00.4 16384 32768 C0.6 0.6 0.8 0.2 49152 65535 2753 g01 v dd = 5v v ref = 5v 10v range code 0 C1.0 dnl (lsb) C0.8 C0.4 C0.2 0.0 1.00.4 16384 32768 C0.6 0.6 0.8 0.2 49152 65535 2753 g02 v dd = 5v v ref = 5v 10v range temperature (c) C40 C1.0 inl (lsb) C0.8 C0.4 C0.2 0.0 1.00.4 C20 20 0 40 C0.6 0.6 0.8 0.2 60 80 2753 g04 v dd = 5v v ref = 5v 10v range +inl Cinl temperature (c) C40 C1.0 dnl (lsb) C0.8 C0.4 C0.2 0.0 1.00.4 C20 20 0 40 C0.6 0.6 0.8 0.2 60 80 2753 g05 v dd = 5v v ref = 5v 10v range +dnl Cdnl temperature (c) C40 bze (lsb) 8 4 2 0 4 C20 20 0 40 6 6 8 2 60 80 2753 g06 v dd = 5v v ref = 5v 10v range 0.5ppm/c (typ) temperature (c) C40 ge (lsb) C16 C8 C4 0 8 C20 20 0 40 C12 12 16 4 60 80 2753 g07 v dd = 5v v ref = 5v 10v range 0.6ppm/c (typ) v ref (v) C10 C8 0 4 4 C6 2 2 6 8 10 2753 g08 v dd = 5v 5v range C1.0 inl (lsb) C0.8 C0.4 C0.2 0.0 1.00.4 C0.6 0.6 0.8 0.2 +inl Cinl +inl Cinl inl vs temperature dnl vs temperature bipolar zero vs temperature gain error vs temperature inl vs v ref dnl vs v ref typical performance characteristics integral nonlinearity (inl) differential nonlinearity (dnl) ltc2753-16 t a = 25c, unless otherwise noted. downloaded from: http:///
ltc2753 8 2753f 500ns/div upd 5v/div gated settling waveform 250v/div 2753 g10 using lt1469 ampc feedback = 12pf 0v to 10v step code 0 C1.0 inl (lsb) C0.8 C0.4 C0.2 0.0 1.00.4 4096 8192 C0.6 0.6 0.8 0.2 12288 16383 2753 g11 v dd = 5v v ref = 5v 10v range code 0 C1.0 dnl (lsb) C0.8 C0.4 C0.2 0.0 1.00.4 4096 8192 C0.6 0.6 0.8 0.2 12288 16383 2753 g12 v dd = 5v v ref = 5v 10v range code 0 C1.0 inl (lsb) C0.8 C0.4 C0.2 0.0 1.00.4 1024 2048 C0.6 0.6 0.8 0.2 3072 4095 2753 g13 v dd = 5v v ref = 5v 10v range code 0 dnl (lsb) 1024 2048 3072 4095 2753 g14 v dd = 5v v ref = 5v 10v range C1.0 C0.8 C0.4 C0.2 0.0 1.00.4 C0.6 0.6 0.8 0.2 typical performance characteristics settling 0v to 10v integral nonlinearity (inl) differential nonlinearity (dnl) ltc2753-12 ltc2753-16 integral nonlinearity (inl) differential nonlinearity (dnl) ltc2753-14 v dd (v) 2.5 C1.0 inl (lsb) C0.8 C0.4 C0.2 0.0 1.00.4 3 4 3.5 4.5 C0.6 0.6 0.8 0.2 5 5.5 2751 g09b +inl Cinl inl vs v dd t a = 25c, unless otherwise noted. multiplying frequency response vs digital code frequency (hz) 100 C120 attenuation (db) C100 C80 C60 C40 C20 0 1k 10k 100k 1m 2753 g10a 10m all bits off d8d4 d2 d0 d7d1 d3 d9d6 d5 d15d14 d12 d10 d13d11 all bits on unipolar 5v output range lt1469 output amplifier c feedback = 15pf downloaded from: http:///
ltc2753 9 2753f 500ns/div upd 5v/div v out 2mv/div 2753 g15 using an lt1469c feedback = 27pf v dd = 5v v ref = 5v 0v to 5v range 1nv?s (typ) digital input voltage (v) 01 0 supply current (ma) 5 10 15 20 2345 2753 g16 v dd = 5v v dd = 3v v dd (v) 2.5 0.5 logic threshold (v) 0.75 1 1.25 1.5 2 3 3.5 4 4.5 5 5.5 1.75 2753 g17 rising falling update frequency (hz) 10 supply current (ma) 0.1 0.01 1 100k 0.001 0.0001 100 1k 10k 1m 10 2753 g18 v dd = 5v v dd = 3v midscale glitchlogic threshold vs supply voltage supply current vs logic input voltage supply current vs update frequency typical performance characteristics ltc2753-12, ltc2753-14, ltc2753-16 t a = 25c, unless otherwise noted. downloaded from: http:///
ltc2753 10 2753f pin functions r com (pin 1): center tap point for the reference inverting resistors. the 20k reference inverting resistors r1 and r2 are connected internally from r in to r com and from r com to refa, respectively (see block diagram). for normal operation tie r com to the negative input of the external reference inverting ampli? er (see typical applications). r in (pin 2): input resistor r1 of the reference inverting resistors. the 20k resistor r1 is connected internally from r in to r com . for normal operation tie r in to the external reference voltage v ref . typically 5v; accepts up to 15v. s2 (pin 3): span i/o bit 2. pins s0, s1 and s2 are used to program and to read back the output ranges of the dacs. i out2a (pin 4): dac a current output complement. tie i out2a to ground. gnd (pin 5): shield ground, provides necessary shielding for i out2a . tie to ground. d3-d11 (pins 6-14): ltc2753-12 only. dac input/output data bits. these i/o pins set and read back the dac code. d11 is the msb. d5-d13 (pins 6-14): ltc2753-14 only. dac input/output data bits. these i/o pins set and read back the dac code. d13 is the msb. d7-d15 (pins 6-14): ltc2753-16 only. dac input/output data bits. these i/o pins set and read back the dac code. d15 is the msb. v dd (pin 15): positive supply input 2.7v v dd 5.5v. requires a 0.1f bypass capacitor to gnd. nc (pin 16): no internal connection. a1 (pin 17): dac address bit 1. see table 3. a0 (pin 18): dac address bit 0. see table 3. gnd (pin 19): ground. tie to ground. clr (pin 20): asynchronous clear. when clr is taken to a logic low, the data registers are reset to the zero-volt code for the present output range (v out = 0v). mspan (pin 21): manual span control pin. mspan is used to con? gure the ltc2753 for operation in a single, ? xed output range. when con? gured for single-span operation, the output range is set via hardware pin strapping. the input and dac registers of the span i/o port are transparent and do not respond to write or update commands. to con? gure the part for single-span use, tie mspan directly to v dd . if mspan is instead connected to gnd (softspan con? guration), the output ranges are set and veri? ed by using write, update and read operations. see manual span con? guration in the operation section. mspan must be connected either directly to gnd (softspan con? guration) or v dd (single-span con? guration). d0-d2 (pins 22-24): ltc2753-12 only. dac input/output data bits. these i/o pins set and read back the dac code. d0 is the lsb. d0-d4 (pins 22-26): ltc2753-14 only. dac input/output data bits. these i/o pins set and read back the dac code. d0 is the lsb. d0-d6 (pins 22-28): ltc2753-16 only. dac input/output data bits. these i/o pins set and read back the dac code. d0 is the lsb. nc (pins 25-30): ltc2753-12 only. no internal connection. nc (pins 27-30): ltc2753-14 only. no internal connection. nc (pins 29, 30): ltc2753-16 only. no internal con- nection.gnd (pin 31): shield ground, provides necessary shielding for i out2b . tie to ground. i out2b (pin 32): dac b current output complement. tie i out2b to ground. s0 (pin 33): span i/o bit 0. pins s0, s1 and s2 are used to program and to read back the output range of the dacs.d /s (pin 34): data/span select. this pin is used to select the data i/o pins or the span i/o pins (d0 to d15 or s0 to s2, respectively), along with their respective dedicated registers, for write or read operations. update operations ignore d /s, since all updates affect both data and span registers. for single-span operation, tie d /s to ground. read (pin 35): read pin. when read is asserted high, the data i/o pins (d0-d15) or span i/o pins (s0-s2) downloaded from: http:///
ltc2753 11 2753f pin functions output the contents of the selected register (see table 1). for single-span operation, readback of the span i/o pins is disabled. upd (pin 36): update and buffer select pin. when read is held low and upd is asserted high, the contents of the addressed dacs input registers (both data and span) are copied into their respective dac registers. the output of the dac is updated, re? ecting the new dac register values. when read is held high, the update function is disabled and the upd pin functions as a buffer selectorlogic low to select the input register, high to select the dac register. see readback in the operation section. wr (pin 37): active low write pin. a write operation cop- ies the data present on the data or span i/o pins (d0-d15 or s0-s2, respectively) into the associated input register. when read is high, the write function is disabled. s1 (pin 38): span i/o bit 1. pins s0, s1 and s2 are used to program and to read back the output ranges of the dacs. refb (pin 39): reference input for dac b. the impedance looking into this pin is 10k to ground. for normal opera-tion tie to the output of the reference inverting ampli? er. typically C5v; accepts up to 15v. r ofsb (pin 40): bipolar offset network for dac b. this pin provides the translation of the output voltage range for bipolar spans. accepts up to 15v; for normal operation tie to the positive reference voltage at r in (pin 2). the impedance looking into this pin is 20k to ground.r fbb (pin 41): dac b feedback resistor. for normal operation tie to the output of the i/v converter ampli? er for dac b (see typical applications). the dac output current from i out1b ? ows through the feedback resistor to the r fbb pin. the impedance looking into this pin is 10k to ground.i out1b (pin 42): dac b current output. this pin is a virtual ground when the dac is operating and should reside at 0v. for normal operation tie to the negative input of the i/v converter ampli? er for dac b (see typical applications). r vosb (pin 43): dac b offset adjust. nominal input range is 5v. the impedance looking into this pin is 1m to ground. if not used, tie r vosb to ground. r vosa (pin 44): dac a offset adjust. nominal input range is 5v. the impedance looking into this pin is 1m to ground. if not used, tie r vosa to ground. i out1a (pin 45): dac a current output. this pin is a virtual ground when the dac is operating and should reside at 0v. for normal operation tie to the negative input of the i/v converter ampli? er for dac a (see typical applications). r fba (pin 46): dac a feedback resistor. for normal operation tie to the output of the i/v converter ampli? er for dac a (see typical applications). the dac output current from i out1a ? ows through the feedback resistor to the rfba pin. the impedance looking into this pin is 10k to ground. r ofsa (pin 47): bipolar offset network for dac a. this pin provides the translation of the output voltage range for bipolar spans. accepts up to 15v; for normal operation tie to the positive reference voltage at r in (pin 2). the impedance looking into this pin is 20k to ground. refa (pin 48): reference input for dac a, and connec- tion for internal reference inverting resistor r2. the 20k resistor r2 is connected internally from r com to refa. for normal operation tie this pin to the output of the reference inverting ampli? er (see typical applications). typically C5v; accepts up to 15v. the impedance looking into this pin is 10k to ground (r in and r com ? oating). exposed pad (pin 49): ground. the exposed pad must be soldered to the pcb. downloaded from: http:///
ltc2753 12 2753f block diagram dac a 16-bit with span select dac b 16-bit with span select 2753 bd 16 3 16 3 16 45 i out1a i out2a i out1b i out2b r vosa r in r1 r2 2 1 48 47 46 r com refa r ofsa r fba r vosb r fbb r ofsb refb mspan read wr upd d /s clr 4 4443 42 39 35 37 36 34 20 21 40 41 32 3 16 3 data dac register span input register data input register span input register control logic data input register i/o port data i /o 6-14, 22-28 span i /o 3, 38, 33 dac address i/o port span dac register data dac register span dac register 16 a1a0 3 1718 downloaded from: http:///
ltc2753 13 2753f timing diagrams write, update and clear timing readback timing clr wr 2753 td01 t 3 t 6 t 5 t 7 t 9 t 8 t 10 t 11 t 12 t 4 t 2 t 1 data/span i/o input upd address a1 - a0 valid valid valid valid d /s t 25 t 26 t 17 d /s wr 2753 td02 t 15 t 18 t 27 t 22 t 20 t 19 t 13 t 23 t 14 t 24 data/span i/o input data/span i/o output upd valid valid valid valid address a1-a0 read downloaded from: http:///
ltc2753 14 2753f output ranges the ltc2753 is a dual current-output, parallel-input preci- sion multiplying dac with software-programmable output ranges. softspan provides two unipolar output ranges (0v to 5v and 0v to 10v), and four bipolar ranges (2.5v, 5v, 10v and C2.5v to 7.5v). these ranges are obtained when an external precision 5v reference is used. when a reference voltage of 2v is used, the softspan ranges become: 0v to 2v, 0v to 4v, 1v, 2v, 4v and C1v to 3v. the output ranges are linearly scaled for references other than 2v and 5v. digital section the ltc2753 has 4 internal registers for each dac, a total of 8 registers (see block diagram). each dac channel has two sets of double-buffered registersone set for the data, and one set for the span (output range) of the dac. the double-buffered feature provides the capability to simulta- neously update the span and code, which allows smooth voltage transitions when changing output ranges. it also permits the simultaneous updating of multiple dacs. each set of double-buffered registers comprises an input register and a dac register. the input registers are holding bufferswhen data is loaded into an input register via a write operation, the dac outputs are not affected. the contents of a dac register, on the other hand, di- rectly control the dac output voltage or output range. the contents of the dac registers are changed by copying the contents of an input register into its associated dac register via an update operation. write and update operations the data input register of the addressed dac is loaded directly from a 16-bit microprocessor bus by holding the d /s pin low and pulsing the wr pin low (write operation). the dac register is loaded by pulsing the upd pin high (update operation), which copies the data held in the input register into the dac register. note that updates always include both data and span; but the dac register values will not change unless the input register values have previ- ously been changed via a write operation. loading the span input register is accomplished similarly, holding the d /s pin high and bringing the wr pin low. the span and data register structures are the same except for the number of parallel bitsthe span registers have 3 bits, while the data registers have 12, 14, or 16. to make both registers transparent for ? owthrough mode, tie wr low and upd high. however, this defeats the deglitcher operation and output glitch impulse may increase. the deglitcher is activated on the rising edge of the upd pin. the interface also allows the use of the input and dac registers in a master-slave, or edge-triggered, con? gura- tion. this mode of operation occurs when wr and upd are tied together and driven by a single clock signal. the data bits are loaded into the input register on the falling edge of the clock and then loaded into the dac register on the rising edge. it is possible to control both data and span on one 16-bit wide data bus by allowing span pins s2 to s0 to share bus lines with the data lsbs (d2 to d0). no write or read operation includes both span and data, so there cannot be a con? ict. the asynchronous clear pin resets both dacs to 0v in any output range. clr resets all data registers, while leaving the span registers undisturbed. operation figure 1. using mspan to con? gure the ltc2753 for single-span operation (10v range). ltc2753-16 mspan s2 s1 s0 d /s dac b dac a 2753 f01 wr upd read a1 a0 data i/o 16 v dd v dd downloaded from: http:///
ltc2753 15 2753f operation the d /s pin. the selected i/o ports pins become logic outputs during readback, while the unselected i/o ports pins remain high-impedance inputs. with the dac channel and i/o port selected, assert read high and select the desired input or dac register using the upd pin. note that upd is a two function pinthe update function is only available when read is low. when read is high, the update function is disabled and the upd pin instead selects the input or dac register for readback. table 1 shows the readback functions for the ltc2753. table 1. write, update and read functions read d /s wr upd span i/o data i/o 0 0 0 0 - write to input register 0 0 0 1 - write/update (transparent) 00 10 - - 0 0 1 1 update dac register update dac register 0 1 0 0 write to input register - 0 1 0 1 write/update (transparent) - 01 10 - - 0 1 1 1 update dac register update dac register 1 0 x 0 - read input register 1 0 x 1 - read dac register 1 1 x 0 read input register - 1 1 x 1 read dac register - x = dont carethe most common readback task is to check the contents of an input register after writing to it, before updating the new data to the dac register. to do this, hold upd low and assert read high. the contents of the selected ports input register are output to its i/o pins. to read back the contents of a dac register, hold upd low and assert read high, then bring upd high to select the dac register. the contents of the selected dac register are output by the selected ports i/o pins. note: if no update is desired after the readback operation, upd must be returned low before bringing read low; otherwise the upd pin will revert to its primary function and update the dac. these devices also have a power-on reset that initializes both dacs to v out = 0v in any output range. the dacs power up in the 0v-5v range if the part is in softspan con? guration; for manual span (see manual span con? gu- ration below), both dacs power up in the manually-chosen range at the appropriate code. manual span con? guration multiple output ranges are not needed in some applications. to con? gure the ltc2753 for single-span operation, tie the mspan pin to v dd and the d /s pin to gnd. the desired output range is then speci? ed by the span i/o pins (s0, s1 and s2) as usual, but the pins are programmed by ty- ing directly to gnd or v dd (see figure 1 and table 2). in this con? guration, both dac channels will initialize to the chosen output range at power-up, with v out = 0v. when con? gured for manual span operation, span pin readback is disabled.readback the contents of any one of the 8 interface registers can be read back from the i/o ports. the i/o pins are grouped into two ports: data and span. the data i/o port comprises pins d0-d11, d0-d13 or d0-d15 (ltc2753-12, ltc2753-14 or ltc2753-16, respectively). the span i/o port comprises pins s0, s1 and s2 for all parts. each dac channel has a set of data registers that are controlled and read back from the data i/o port; and a set of span registers that are controlled and read back from the span i/o port. the register structure is shown in the block diagram. a readback operation is initiated by asserting read to logic high after selecting the desired dac channel and i/o port. the i/o pins, which are high-impedance digital inputs when read is low, selectively change to low-impedance logic outputs during readback. select the dac channel with address pins a1 and a0, and select the i/o port (data or span) to be read back with downloaded from: http:///
ltc2753 16 2753f system offset adjustmentmany systems require compensation for overall system offset. the r vosa and r vosb offset adjustment pins are provided for this purpose. for noise immunity and ease of adjustment, the control voltage is attenuated to the dac output: v os = C0.01 ? v(r vosx ) [0v to 5v, 2.5v spans] v os = C0.02 ? v(r vosx ) [0v to 10v, 5v, C2.5v to 7.5v spans]v os = C0.04 ? v(r vosx ) [10v span] the nominal input range of this pin is 5v; other reference voltages of up to 15v may be used if needed. the r vosx pins have an input impedance of 1m. to preserve the settling performance of the ltc2753, drive this pin with a thevenin-equivalent impedance of 10k or less. short any unused system offset adjustment pins to i out2 . table 2. span codes s2 s1 s0 span 0 0 0 unipolar 0v to 5v 0 0 1 unipolar 0v to 10v 0 1 0 bipolar C5v to 5v 0 1 1 bipolar C10v to 10v 1 0 0 bipolar C2.5v to 2.5v 1 0 1 bipolar C2.5v to 7.5v codes not shown are reserved and should not be used. table 3. address codes dac channel a1 a0 a0 0 b0 1 all* 1 1 codes not shown are reserved and should not be used. *if readback is taken using the all dacs address, the ltc2753 defaults to dac a. operation downloaded from: http:///
ltc2753 17 2753f operation examples wr 2753 td03 span i/o input data i/o input upd d /s 8000 h 010 read = low update(5v range, v out = 0v) wr 2753 td04 span i/o input data i/o input read = low upd d /s c000 h 4000 h 011 update (5v) update (C5v) wr 2753 td05 data i/o output data i/o input read upd d /s 8000 h 8000 h 0000 h hi-z input register dac register hi-z update (2.5v) 1. load 5v range with the output at 0v. note that since span and code are updated together, the output, if started at 0v, will stay there. the 16-bit dac code is shown in hex for compactness. 2. load 10v range with the output at 5v, changing to C5v. 3. write and update midscale code in 0v to 5v range (v out = 2.5v) using readback to check the contents of the input and dac registers before updating. downloaded from: http:///
ltc2753 18 2753f op amp selectionbecause of the extremely high accuracy of the 16-bit ltc2753-16, careful thought should be given to op amp selection in order to achieve the exceptional performance of which the part is capable. fortunately, the sensitivity of inl and dnl to op amp offset has been greatly reduced compared to previous generations of multiplying dacs. tables 4 and 5 contain equations for evaluating the effects of op amp parameters on the ltc2753s accuracy when applications information programmed in a unipolar or bipolar output range. these are the changes the op amp can cause to the inl, dnl, unipolar offset, unipolar gain error, bipolar zero and bipolar gain error. tables 4 and 5 can also be used to determine the effects of op amp parameters on the ltc2753-14 and the ltc2753-12. however, the results obtained from tables 4 and 5 are in 16-bit lsbs. divide these results by 4 (ltc2753-14) and 16 (ltc2753-12) to obtain the correct lsb sizing. table 6 contains a partial list of ltc precision op amps recommended for use with the ltc2753. the easy-to-use design equations simplify the selection of op amps to meet the systems speci? ed error budget. select the ampli? er from table 6 and insert the speci? ed op amp parameters in table 5. add up all the errors for each category to de- termine the effect the op amp has on the accuracy of the part. arithmetic summation gives an (unlikely) worst-case effect. a root-sum-square (rms) summation produces a more realistic estimate. () 5v v ref () 5v v ref () 16.5k a vol1 op amp v os1 (mv) i b1 (na) a vol1 (v/v) v os2 (mv) i b2 (mv) a vol2 (v/v) v os1 ? 3.2 ? i b1 ? 0.0003 ?? a1 ? 0 0 0 inl (lsb) () 5v v ref () 5v v ref () 1.5k a vol1 () 66k a vol2 () 131k a vol1 () 131k a vol1 () 131k a vol2 () 131k a vol2 v os1 ? 0.82 ? i b1 ? 0.00008 ?? a2 ? 0 0 0 dnl (lsb) () 5v v ref () 5v v ref a3 ? v os1 ? 13.2 ? i b1 ? 0.13 ?? 0 0 0 0 unipolar offset (lsb) () 5v v ref () 5v v ref () 5v v ref v os1 ? 13.2 ? i b1 ? 0.0018 ? a5 ? v os2 ? 26.2 ? i b2 ? 0.26 ? bipolar gain error (lsb) () 5v v ref () 5v v ref () () () 5v v ref () 5v v ref a3 ? v os1 ? 19.8 ? i b1 ? 0.13 ?? 0 a4 ? v os2 ? 13.1 ? a4 ? i b2 ? 0.13 ?? a4 ? bipolar zero error (lsb) unipolar gain error (lsb) () 5v v ref () 5v v ref () 5v v ref () 5v v ref () 5v v ref v os1 ? 13.2 ? i b1 ? 0.0018 ? a5 ? v os2 ? 26.2 ? i b2 ? 0.26 ? table 4. variables for each output range that adjust the equations in table 5 output range a1 a2 a3 a4 a5 5v 1.1 2 1 1 10v 2.2 3 0.5 1.5 5 v 22111 . 5 10v 4 4 0.83 1 2.5 2.5v 1 1 1.4 1 1 C2.5v to 7.5v 1.9 3 0.7 0.5 1.5 table 6. partial list of ltc precision ampli? ers recommended for use with the ltc2753 with relevant speci? cations amplifier amplifier specifications v os v i b na a vol v/mv voltage noise nv/ ? h ? z current noise pa/ ? h ? z slew rate v/s gain bandwidth product mhz t settling with ltc2753 s power dissipation mw lt1001 25 2 800 10 0.12 0.25 0.8 120 46 lt1097 50 0.35 1000 14 0.008 0.2 0.7 120 11 lt1112 (dual) 60 0.25 1500 14 0.008 0.16 0.75 115 10.5/op amp lt1124 (dual) 70 20 4000 2.7 0.3 4.5 12.5 19 69/op amp lt1468 75 10 5000 5 0.6 22 90 2 117 lt1469 (dual) 125 10 2000 5 0.6 22 90 2 123/op amp table 5. easy-to-use equations determine op amp effects on dac accuracy in all output ranges (circuit of page 1). subscript 1 refers to output amp, subscript 2 refers to reference inverting amp. downloaded from: http:///
ltc2753 19 2753f applications information op amp offset will contribute mostly to output offset and gain error, and has minimal effect on inl and dnl. for example, for the ltc2753-16 with a 5v reference in 5v unipolar mode, a 250v op amp offset will cause a 3.3lsb zero-scale error and a 3.3lsb gain error; but only 0.8lsb of inl degradation and 0.2lsb of dnl degradation. while not directly addressed by the simple equations in tables 4 and 5, temperature effects can be handled just as easily for unipolar and bipolar applications. first, consult an op amps data sheet to ? nd the worst-case v os and i b over temperature. then, plug these numbers in the v os and i b equations from table 5 and calculate the tempera- ture-induced effects.for applications where fast settling time is important, ap- plication note 74, component and measurement advances ensure 16-bit dac settling time, offers a thorough discus- sion of 16-bit dac settling time and op amp selection. precision voltage reference considerations much in the same way selecting an operational ampli? er for use with the ltc2753 is critical to the performance of the system, selecting a precision voltage reference also requires due diligence. the output voltage of the ltc2753 is directly affected by the voltage reference; thus, any voltage reference error will appear as a dac output volt- age error. there are three primary error sources to consider when selecting a precision voltage reference for 16-bit appli- cations: output voltage initial tolerance, output voltage temperature coef? cient and output voltage noise. initial reference output voltage tolerance, if uncorrected, generates a full-scale error term. choosing a reference with low output voltage initial tolerance, like the lt1236 (0.05%), minimizes the gain error caused by the reference; however, a calibration sequence that corrects for system zero- and full-scale error is always recommended. a references output voltage temperature coef? cient af- fects not only the full-scale error, but can also affect the circuits apparent inl and dnl performance. if a refer- ence is chosen with a loose output voltage temperature coef? cient, then the dac output voltage along its transfer characteristic will be very dependent on ambient conditions. minimizing the error due to reference temperature coef- ? cient can be achieved by choosing a precision reference with a low output voltage temperature coef? cient and/or tightly controlling the ambient temperature of the circuit to minimize temperature gradients. as precision dac applications move to 16-bit and higher performance, reference output voltage noise may con- tribute a dominant share of the systems noise ? oor. this in turn can degrade system dynamic range and signal-to- noise ratio. care should be exercised in selecting a voltage reference with as low an output noise voltage as practi- cal for the system resolution desired. precision voltage references, like the lt1236, produce low output noise in the 0.1hz to 10hz region, well below the 16-bit lsb level in 5v or 10v full-scale systems. however, as the circuit bandwidths increase, ? ltering the output of the reference may be required to minimize output noise. table 7. partial list of ltc precision references recommended for use with the ltc2753 with relevant speci? cations reference initial tolerance temperature drift 0.1hz to 10hz noise lt1019a-5, lt1019a-10 0.05% 5ppm/c 12v p-p lt1236a-5, lt1236a-10 0.05% 5ppm/c 3v p-p lt1460a-5, lt1460a-10 0.075% 10ppm/c 20v p-p lt1790a-2.5 0.05% 10ppm/c 12v p-p downloaded from: http:///
ltc2753 20 2753f grounding as with any high resolution converter, clean grounding is important. a low impedance analog ground plane and star grounding techniques should be used. i out2 must be tied to the star ground with as low a resistance as possible. when it is not possible to locate star ground close to i out2 , a low resistance trace should be used to route this applications information pin to star ground. this minimizes the voltage drop from this pin to ground caused by the code dependent current ? owing to ground. when the resistance of this circuit board trace becomes greater than 1, a force/sense am- pli? er con? guration should be used to drive this pin (see figure 2). this preserves the excellent accuracy (1lsb inl and dnl) of the ltc2753-16. downloaded from: http:///
ltc2753 21 2753f applications information C + C + 1/2 lt1469 1/2 lt1469 dac a ltc2753-16 v ref 5v 2 1 3 45 46 472 1 1 48 i out1a 15pf i out2a r fba r vosa refa r com r in r ofsa v outa 4 44 C + 6 123 i out2 23 *schottky barrier diode zetex* bat54s lt1001 2753 f02 1000pf alternate amplifier for optimum settling time performance 6 123 4,32 C + lt1468 3 zetex bat54s 2 200 200 i out2 150pf 32 figure 2. optional circuits for driving i out2 from gnd with a force/sense ampli? er. downloaded from: http:///
ltc2753 22 2753f C + C + 1/2 lt1469 1/2 lt1469 dac adac b ltc2753-16 v ref 5v 2 1 3 45 46 472 1 1 r1r2 48 i out1a i out2b i out1b 15pf15pf c2c3 i out2a r fba r vosa r vosb r fbb refa 39 wr upd read d /s clr wr upd read d /s clr mspan address *for multiplying applications c1 = 15pf a1, a0 refb 40 37 36 35 34 20 21 17, 18 r ofsb r com r in r ofsa v outa 4 4443 32 42 41 2753 f03 150pf c1* data i/o d15 - d0 span i/o s2 - s0 32 + C 1/2 lt1469 5 7 6 v outb 16 3 i/o port i/o port dual 16-bit v out dac with software-selectable ranges typical applications downloaded from: http:///
ltc2753 23 2753f information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. package description uk package 48-lead plastic qfn (7mm 7mm) (reference ltc dwg # 05-08-1704 rev c) 7.00 0.10 (4 sides) note:1. drawing conforms to jedec package outline mo-220 variation (wkkd-2) 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.20mm on any side, if present 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 top mark(see note 6) pin 1 chamfer c = 0.35 0.40 0.10 48 47 12 bottom view?xposed pad 5.50 ref (4-sides) 0.75 0.05 r = 0.115 typ 0.25 0.05 0.50 bsc 0.200 ref 0.00 ?0.05 (uk48) qfn 0406 rev c recommended solder pad pitch and dimensions apply solder mask to areas that are not soldered 0.70 0.05 5.50 ref (4 sides) 6.10 0.05 7.50 0.05 0.25 0.05 0.50 bsc package outline 5.15 0.10 5.15 0.10 5.15 0.05 5.15 0.05 r = 0.10 typ downloaded from: http:///
ltc2753 24 2753f linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ? linear technology corporation 2007 lt 1007 printed in usa related parts typical application part number description comments lt1027 precision reference 1ppm/c maximum drift lt1236a-5 precision reference 0.05% maximum tolerance, 1ppm 0.1hz to 10hz noise lt1468 16-bit accurate op-amp 90mhz gbw, 22v/s slew rate lt1469 dual 16-bit accurate op-amp 90mhz gbw, 22v/s slew rate ltc1588/ltc1589/ ltc1592 serial 12-/14-/16-bit i out single dac software-selectable (softspan) ranges, 1lsb inl, dnl, 16-lead ssop package ltc1591/ltc1597 parallel 14-/16-bit i out single dac integrated 4-quadrant resistors ltc1821 parallel 16-bit v out single dac 1lsb inl, dnl, 0v to 10v, 0v to C10v, 10v output ranges ltc2601/ltc2611/ ltc2621 serial 12-/14-/16-bit v out single dacs single dacs, spi-compatible, single supply, 0v to 5v outputs in 3mm 3mm dfn-10 package ltc2606/ltc2616/ ltc2626 serial 12-/14-/16-bit v out single dacs single dacs, i 2 c-compatible, single supply, 0v to 5v outputs in 3mm 3mm dfn-10 package ltc2641/ltc2642 serial 12-/14-/16-bit unbuffered v out single dacs 2lsb inl, 1lsb dnl, 1s settling, tiny msop-10, 3mm 3mm dfn-10 packages ltc2704 serial 12-/14-/16-bit v out quad dacs software-selectable (softspan) ranges, integrated ampli? ers, 2lsb inl ltc2751 parallel 12-/14-/16-bit i out softspan single dacs 1lsb inl, dnl, software-selectable (softspan) ranges, 5mm 7mm qfn-38 package C + u2a lt ? 1469 C + u4b lt1469 ltc2753-16 u1 lt1027 u3 r vosa r vosb r com r in r ofsb r ofsa 2 1 3 8 33 4 21 6 7 5 84 in out trim gnd v + v + v C refa refb r fba r fbb i out1a i out2b i out1b v outa 46 4543 4432 42 i out2a data i/o span i/o d15d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 s2 s1 s0 4 67 8 9 1011 12 13 14 22 23 24 25 26 27 28 3 3833 4 22 1 65 c22 0.001 f c1 30pf v dd 2753 ta03 r1 10k offset trim a offset trim b 21 r310k c2 30pf wr upd read d /s clr mspan 34 35 36 37 20 21 wr upd read d /s clr gnd gnd gnd gnd 51 9 31 49 41 15 47 40 2 1 48 39 c230.1f c20 10f c1310f gaintrim r210k + C u4a lt1469 3 1 2 v outb v + v C offset and gain trim circuits. powering v dd from lt1027 ensures quiet supply downloaded from: http:///

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